Please use this identifier to cite or link to this item: https://hdl.handle.net/10216/101189
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dc.creatorRicardo Ferreira
dc.creatorAlisson Garcia
dc.creatorTiago Teixeira
dc.creatorJoão M. P. Cardoso
dc.date.accessioned2022-09-11T11:10:37Z-
dc.date.available2022-09-11T11:10:37Z-
dc.date.issued2007
dc.identifier.othersigarra:70866
dc.identifier.urihttps://hdl.handle.net/10216/101189-
dc.description.abstractCoarse-grained reconfigurable computing architectures vary widely in the number and characteristics of the processing elements (cells) and routing topologies used. In order to exploit several different topologies, a place and route framework, able to deal with such vast design exploration space, is of paramount importance. Bearing this in mind, this paper proposes a placement scheme able to target different topologies when considering data-driven reconfigurable architectures. Our approach uses graph models for the target architecture and for the dataflow representation of the application being mapped. Our placement algorithm is guided by a Depth-First Traversal in both the architecture and the application graphs. Two versions of the placement algorithm with respectively O(e) and O(e + n(3)) computational complexities are presented, where e is the number of edges in the dataflow representation of the application and n is the number of cells in the graph model of the architecture. The achieved experimental results show that our approach can be useful to exploit different interconnect topologies as far as coarse-grained reconfigurable computing architectures are concerned.
dc.language.isoeng
dc.relation.ispartofIEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: EMERGING VLSI TECHNOLOGIES AND ARCHITECTURES
dc.rightsrestrictedAccess
dc.subjectEngenharia de computadores, Engenharia electrotécnica, electrónica e informática
dc.subjectComputer engineering, Electrical engineering, Electronic engineering, Information engineering
dc.titleA polynomial placement algorithm for data driven coarse-grained reconfigurable architectures
dc.typeArtigo em Livro de Atas de Conferência Internacional
dc.contributor.uportoFaculdade de Engenharia
dc.identifier.doi10.1109/isvlsi.2007.14
dc.identifier.authenticusP-007-JVC
dc.subject.fosCiências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática
dc.subject.fosEngineering and technology::Electrical engineering, Electronic engineering, Information engineering
Appears in Collections:FEUP - Artigo em Livro de Atas de Conferência Internacional

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